As the speed and file capacity of workstations in personal computers increases, the demand for high resolution intelligent display adapters also increases. Large graphic applications formerly limited to mainframe computers having dedicated graphic display terminals can use this increased capability in the adapters to migrate their graphic applications to stand alone systems. The present invention describes functions that can be incorporated into a video display adapter to provide, in stand alone workstations, the graphic functions and performance required by such complex graphic applications.
Such increased capability display adapters are especially needed for such small stand alone systems as the IBM PC/AT and the IBM RT-PC which can provide high-performance, moderatecost adapter functions which cover a very broad spectrum of applications.
The principle role of the pixel data path is to provide a host processor with a convenient access to frame buffer date. There are several problems which usually are not solved fully by the existing approach to the architecture of such a data path.
The frame buffer architecture usually supports either the pixel or plane structure of an image. It means that the conventional architecture provides good performance only for a particular area of application.
Thus, for a pixel oriented architecture, (e.g., image processing applications) several pixels are conventionally accessed in parallel, but only the same number of bits in one plane can be processed. So, performance for plane oriented applications is usually low because the frame buffer I/O width can not be fully utilized.
For plane oriented systems (e.g., 2.5 D graphics) multi-bit data from the same plane can be easily accessed, but for applications, requiring pixel access, a number of memory cycles must be used to access a pixel.
The representation of data for the host processor depends on the application. Taking a 32-bit host processor, for example, a processor word can stand for four (8 bit) pixels for pixeloriented applications, or for 32 bits of the same plane for planeoriented problems or for a corresponding number of pixel "slices" for processing pixel data fields.
If the host data bus is "hard-wired" to a frame buffer, the host must rearrange words, placing bits in relation to the frame buffer I/O layout.
The conventional idea of the bit block transfer (bit-blt) primitive, J. D. Foley, A. Van Dam, "FUNDAMENTALS OF INTERACTIVE COMPUTER GRAPHICS", Addison-Wesley, Reading, MA. 1982, pp. 465, 484-485, allows increased performance only for simple area copy or logical operations between planes. Briefly and simply stated this operation comprises the parallel access of the frame buffer to a plurality of contiguous pixels making up a block of video data. The operation speeds certain display operations. The incorporation of arithmetic operations into the bit-blt hardware has been tried but has generally proved useless for color graphics, so the processing of colors has usually been done by the host. But in the area of color graphics there is a very important application, specifically a fast antialiasing copy of characters or vectors, Paul N. Sholtz, "MAKING HIGH-QUALITY COLORED IMAGES ON RASTER DISPLAYS", Research Report RC9632, available from the library of the IBM Thomas J. Watson Research Center, Yorktown Heights, New York 1982. This operation provides a very high quality of text (or graphics) on even a low resolution screen, and in the case of a restricted number of colors (e.g., 16 for background and 16 for characters) requires only simple and uniform arithmetic operations on pixel intensity and color attributes.
An all-point addressable frame buffer (such as described in copending Application Ser. No. 07/013,843 filed Feb. 12, 1987 requires a certain kind of data alignment, which is able to provide a proper order of bits in the accessed word independently of its address, Rober F. Sproull, Ivan E. Sutherland, Alistair Thompson, Satish Gupta, and Charles Minter, "THE 8 BY 8 DISPLAY", ACM Trans. Graphics, Vol. 2, No. 1, Jan. 1983, pp. 32-56.
The host processor may handle such an operation but in the time-consuming and application dependent manner. The present invention provides a special alignment unit which makes this alignment invisible for the user.
With the use of 1-Meg memory chips, now appearing on the market, the performance for plane-oriented operations may be reduced drastically due to the narrower frame buffer data width. E.g., with the use of 256 K chips (64K by 4), the data path may be 4 times wider than is the case with 1 Meg chips (256K by 4).